This invention relates to data processing in general and more particularly, to a reconfigurable bus for use in a data processing system, which bus can be configured to either communicate with external memory or external I/O such as an additional processor.
The need for large amounts of memory in modern day processors is well recognized. It is also recognized that it is desirable to provide memory in variable amounts. To accomplish this, additional memory can be provided and accessed by means of a memory bus. In accordance with a system of the type disclosed in the present application, such a memory bus includes a configuration bus which provides information to the computer system concerning the configuration of the memory. Another requirement in computer systems which is becoming increasingly important is the ability to interface with other computer systems. Typically this is done over an I/O bus. In conventional systems, separate hardware is provided to implement separate memory buses and I/O buses. This becomes a particular problem when trying to place all of the necessary hardware on a single board. However, in some instances, both the I/O bus access and memory access are not needed at the same time. Thus, it would be beneficial if a single bus could be used for both purposes, despite the fact that the two types of devices, i.e. memory and I/O device, e.g. another processor have somewhat different requirements.